One view of a vector register size is 64 64-bit data elements, but 128 32-bit elements, 256 16-bit elements, and even 512 8-bit elements are equally valid views. Vectors naturally accommodate varying data sizes (hardware multiplicity). The independence of elements within a vector instruction set allows scaling of functional units without performing additional costly dependency checks, as superscalar processors require. Vector designs use slow but wide execution units to achieve high performance at low power. Vector instructions operate on many elements simultaneously. These memory locations are accessed through an address generator.
In the figure below, a vector register points to a vector of length. Each vector register is a fixed-length bank holding a single vector. Memory SystemĪ microprocessor has a set of vector registers. Vector programs strive to keep memory busy. Since vector loads and stores are deeply pipelined, the program pays the long memory latency only once per vector load or store versus once per element, thus amortizing the latency over, say, 64 elements. A single instruction operates on vectors of data, which results in dozens of register–register operations on independent data elements. Vector architectures grab sets of data elements scattered about memory, place them into large, sequential register files, operate on data in those register files, and then disperse the results back into memory.
The programmer continues to think sequentially yet achieves parallel speedup by having parallel data operations. Vector architecture is a variant of SIMD (single instruction multiple data), a single instruction can launch many data operations.
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